 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| the sa828 pwm generator has been designed to provide waveforms for the control of variable speed ac machines, uninterruptible power supplies and other forms of power electronic devices which require pulse width modulation as a means of efficient power control. the six ttl level pwm outputs (fig. 2) control the six switches in a three-phase inverter bridge. this is usually via an external isolation and amplification stage. the sa828 is fabricated in cmos for low power consumption. information contained within the pulse width modulated sequences controls the shape, power frequency, amplitude, and rotational direction (as defined by the red-yellow-blue phase sequence) of the output waveform. parameters such as the carrier frequency, minimum pulse width, and pulse delay time may be defined during the initialisation of the device. the pulse delay time (underlap) controls the delay between turning on and off the two power switches in each output phase of the inverter bridge, in order to accommodate variations in the turn- on and turn-off times of families of power devices. the sa828 is easily controlled by a microprocessor and its fully-digital generation of pwm waveforms gives unprecedented accuracy and temperature stability. precision pulse shaping capability allows optimum efficiency with any power circuitry. the device operates as a stand-alone microprocessor peripheral, reading the power waveform directly from an internal rom and requiring microprocessor intervention only when operating parameters need to be changed. an 8-bit multiplexed data bus is used to receive addresses and data from the microprocessor/controller. this is a standard motel tm bus, compatible with most microprocessors/controllers. rotational frequency is defined to 12 bits for high accuracy and a zero setting is included in order to implement dc injection braking with no software overhead. this family is pin and functionally compatible with the ma828 pwm generator . two standard wave shapes are available to cover most applications. in addition, any symmetrical wave shape can be integrated on-chip to order. features n fully digital operation n interfaces with most microprocessors n wide power-frequency range n 12-bit speed control accuracy n carrier frequency selectable up to 24khz n waveform stored in internal rom n double edged regular sampling n selectable minimum pulse width and underlap time n dc injection braking dp28 mp28 fig. 1 pin connections C top view (not to scale) motel is a registered trademark of intel corp. and motorola corp. ad 2 ad 1 ad 0 vdd zppb zppy zppr wss rpht set trip ypht bpht v ss bphb ad 3 ad 4 ad 5 ad 6 ad 7 wr* (r/w?) rd* (ds?) ale* (as?) rst clk cs trip rphb yphb * = intel bus format ? = motorola bus format 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sa828 sa828 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ad 2 ad 1 ad 0 vdd zppb zppy zppr wss rpht set trip ypht bpht v ss bphb ad 3 ad 4 ad 5 ad 6 ad 7 wr* (r/w?) rd* (ds?) ale* (as?) rst clk cs trip rphb yphb ordering information sa8281/ig/dp1s (28-lead dil, sine + third harmonic waveform) sa8282/ig/dp1s (28-lead dil, sine waveform) sa8281/ig/mp1s (28-lead soic, sine + third harmonic waveform) sa8382/ig/mp1s (28-lead soic, sine waveform) sa828 family three-phase pwm waveform generator ds4226 - 2.0 november 1996
sa828 2 >45 <02 <10 50 input high voltage input low voltage input leakage current output high voltage output low voltage supply current (static) supply current (dynamic) supply voltage v in = v ss or v dd i oh = C 12ma i ol = 12ma all outputs open circuit f clk = 10mhz v ih v il i in v oh v ol i dd (static) i dd (dynamic) v dd 2 40 45 08 10 04 100 20 55 typ. max. min. value characteristic symbol conditions units electrical characteristics these characteristics are guaranteed over the following conditions (unless otherwise stated): v dd = +5v 5%, t amb = +25 c dc characteristics v v m a v v m a ma v - 2/f clk 2/f clk clock frequency clock duty cycle set trip = 1 ? outputs tripped ? trip = 0 m : s ratio = 1 : 1 20% f clk in mhz f clk in mhz f clk d clk t trip 125 60 3/f clk 3/f clk mhz % m s m s note 1. for microprocessor interface timings, see intel and motorola bus timings (tables 1 and 2). conditions typ. max. characteristic symbol units value ac characteristics absolute maximum ratings supply voltage, v dd voltage on any pin current through any i/o pin storage temperature operating temperature range pin no. 1 2 3 4 5 6 7 8 9 10 11 12 name ad 3 ad 4 ad 5 ad 6 ad 7 intel: wr motorola: r/ w intel: rd motorola: ds intel: ale motorola: as rst clk cs trip type i i i i i i i i i i i o function multiplexed address/data multiplexed address/data multiplexed address/data multiplexed address/data multiplexed address/data(msb) intel bus control: write strobe motorola bus control: read/ write select intel bus control: read strobe motorola bus control: data strobe intel bus control: address latch enable motorola bus control: address strobe reset internal counters, active low clock input chip select input, active low output trip status; low = output tripped name rphb yphb bphb v ss bpht ypht set trip rpht wss zppr zppy zppb v dd ad 0 ad 1 ad 2 pin no. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 type o o o p o o i o o o o o p i i i function red phase, bottom power switch yellow phase, bottom power switch blue phase, bottom power switch negative power supply (0v) blue phase, top power switch yellow phase, top power switch set output trip. 120k w internal pull-up resistor red phase, top power switch waveform sampling synchronisation zero phase pulse, red phase zero phase pulse, yellow phase zero phase pulse, blue phase positive power supply multiplexed address/data (lsb) multiplexed address/data multiplexed address/data pin descriptions the temperature ranges quoted apply to all package types. many package types are available and extended temperature 7v v ss C03v to v dd +03v 10ma C65 c to +125 c C40 c to +85 c 40 ranges can be offered for some. further information is available on request. stresses above those listed in the absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 sa828 fig. 2 sa828 internal block diagram pulse deletion pulse delay circuit rpht rphb pulse deletion pulse delay circuit ypht yphb pulse deletion pulse delay circuit bpht bphb red phase yellow phase blue phase phasing and control logic waveform rom trip latch address generator 24-bit initialisation register 24-bit control register r0 r1 r2 r3 r4 bus demultiplexer bus control clock divider rst ? motel interface system bus ad 0 -ad 7 8 set trip trip cs clock zpp o / ps wss functional description an asynchronous method of pwm generation is used with uniform or double-edged regular sampling of the waveform stored in the internal rom as illustrated in fig. 3. the triangle carrier wave frequency is selectable up to 24khz (assuming the maximum clock frequency of 12.5mhz is used), enabling ultrasonic operation for noise critical applications. with 12.5mhz clock, power frequency ranges of up to 4khz are possible, with the actual output frequency resolved to 12-bit accuracy within the chosen range in order to give precise motor speed control and smooth frequency changing. the output phase sequence of the pwm outputs can also be changed to allow both forward and reverse motor operation. pwm output pulses can be tailored to the inverter characteristics by defining the minimum allowable pulse width (the sa828 will delete all shorter pulses from the pure pwm pulse train) and the pulse delay (underlap) time, without the need for external circuitry. this gives cost advantages in both component savings and in allowing the same pwm circuitry to be used for control of a number of different motor drive circuits simply by changing the microprocessor software. power frequency amplitude control is also provided with an overmodulation option to assist in rapid motor braking. alternatively, braking may be implemented by setting the rotational speed to 0hz. this is termed dc injection braking, in which the rotation of the motor is opposed by allowing dc to flow in the windings. a trip input allows the pwm outputs to be shut down immediately, overriding the microprocessor control in the event of an emergency. the waveform sampling synchronisation (wss) output may be used in conjunction with the zpp signals to provide feedback of the actual rotational speed from the rotor. this is of particular use in slip compensated systems. other possible sa828 applications are as a 3-phase waveform generator as part of a switched-mode power supply (smps) or of an uninterruptible power supply (ups). in such applications the high carrier frequency allows a very small switching transformer to be used. microprocessor interface the sa828 interfaces to the controlling microprocessor by means of a multiplexed bus of the motel format. this interface bus has the ability to adapt itself automatically to the format and timing of both motorola and intel interface buses (hence motel). internally, the detection circuitry latches the status of the ds/ rd line when as/ale goes high. if the result is high then the intel mode is used; if the result is low then the motorola mode is used. this procedure is carried out each time that as/ale goes high. in practice this mode selection is transparent to the user. for bus connection and timing information refer to the description relevant to the microprocessor/controller being used. industry standard microprocessors such as the 8085, 8088, etc. and microcontrollers such as the 8051, 8052 and 6805 are all compatible with the interface on the sa828. this interface consists of 8 data lines, ad 0 - ad 7 (write-only in this instance), which are multiplexed to carry both the address and data information, 3 bus control lines, labelled wr, rd and ale in intel mode and r/ w , ds and as in motorola mode, and a chip select input, cs , which allows the sa828 to share the same bus as other microprocessor peripherals. it should be noted that all bus timings are derived from the microprocessor and are independent of the sa828 clock input. sa828 4 fig. 3 asynchronous pwm generation withdouble-edged regular sampling as used by the sa828 t 1 ale t 4 t 3 t 2 t 8 t 10 t 11 t 9 t 12 rd wr ad 0 -ad 7 cs latch address latch data t 15 t 4 t 3 t 8 t 10 t 11 t 9 t 12 ds r / w ad 0 -ad 7 cs latch address latch data t 1 as t 2 t 5 t 6 t 7 t 15 + 1 e 1 + 1 e 1 resulting pwm waveform 0 0 pwm switching instants triangle wave at carrier frequency, sampling on + ve and e ve peaks power waveform as read from internal rom fig. 5 motorola bus timing definitions parameter as high period delay time, as low to ds high ds high period delay time, ds low to as high ds low period ds high to r/ w low setup time r/ w hold time cs setup time cs hold time address setup time address hold time write data setup time write data hold time symbol t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 15 t 11 t 12 min. 90 40 210 40 200 10 10 20 0 30 30 110 30 table 2 motorola bus timings at v dd = 5v, t amb = +25 c units ns ns ns ns ns ns ns ns ns ns ns ns ns fig. 4 intel bus timing definitions parameter ale high period delay time, ale to wr wr low period delay time, wr high to ale high cs setup time cs hold time address setup time address hold time data setup time data hold time symbol t 1 t 2 t 3 t 4 t 8 t 9 t 10 t 15 t 11 t 12 min. 70 40 200 40 20 0 30 30 100 25 table 1 intel bus timings at v dd = 5v, t amb = + 25 c units ns ns ns ns ns ns ns ns ns ns 5 sa828 register r0 r1 r2 r3 r4 comment temporary register r0 temporary register r1 temporary register r2 transfers control data transfers initialisation data ad 1 0 0 1 1 0 power frequency range this sets the maximum power frequency that can be carried within the pwm output waveforms. this would normally be set to a value to prevent the motor system being operated outside its design parameters. pulse delay time ('underlap') for each phase of the pwm cycle there are two control signals, one for the top switch connected to the positive inverter dc supply and one for the bottom switch connected to the negative inverter dc supply. in theory, the states of these two switches are always complementary. however, due to the finite and non-equal turn-on and turn- off times of power devices, it is desirable when changing the state of the output pair, to provide a short delay time during which both outputs are off in order to avoid a short circuit through the switching elements. pulse deletion time a pure pwm sequence produces pulses which can vary in width between 0% and 100% of the duty cycle. therefore, in theory, pulse widths can become infinitesimally narrow. in practice this causes problems in the power switches due to storage effects and therefore a minimum pulse width time is required. all pulses shorter than the minimum specified are deleted. counter reset this facility allows the internal power frequency counter of the sa828 to be set to zero, disabling the normal frequency control and giving a 50% output duty cycle. initialisation register programming the initialisation register data is loaded in 8-bit segments into the three 8-bit temporary registers r0-r2. when all the initialisation data has been loaded into these registers it is transferred into the 24-bit initialisation register by writing to the dummy register r4. ad 2 0 0 0 0 1 ad 0 0 1 0 1 0 table 3 sa828 register addressing initialisation register function the 24-bit initialisation register contains parameters which, under normal operation, will be defined during the power-up sequence. these parameters are particular to the drive circuitry used, and therefore changing these parameters during a pwm cycle is not recommended. information in this register should only be modified while rst is active (i.e. low) so that the pwm outputs are inhibited (low) during the updating process. the parameters set in the initialisation register are as follows: carrier frequency low carrier frequencies reduce switching losses whereas high carrier frequencies increase waveform resolution and can allow ultrasonic operation. carrier frequency selection the carrier frequency is a function of the externally applied clock frequency and a division ratio n , determined by the 3-bit cfs word set during initialisation. the values of n are selected as shown in table 4. the carrier frequency, f carr , is then given by: cfs word value of n 000 1 001 2 010 4 011 8 100 16 101 32 table 4 values of clock division ratio n frs 2 frs 1 frs 0 x x cfs 2 cfs 2 cfs 2 ? ? ? ? ? ? ? ? ? frequency range select word frs 2 = msb frs 0 = lsb dont care carrier frequency select word cfs 2 = msb cfs 0 = lsb fig. 6 temporary register r1 where k = clock frequency and n = 1, 2, 4, 8, 16 or 32 (as set by cfs) power frequency range selection the power frequency range selected here defines the maximum limit of the power frequency. the operating power frequency is controlled by the 12-bit power frequency select (pfs) word in the control register but may not exceed the value set here. k 512 x n f carr = microprocessor bus timing intel mode (fig. 4 and table 1) the address is latched by the falling edge of ale. data is written from the bus into the sa828 on the rising edge of wr. rd is not used in this mode because the registers in the sa828 are write only. however, this pin must be connected to rd (or tied high) to enable the sa828 to select the correct interface format. motorola mode (fig. 5 and table 2) the address is latched on the falling edge of the as line. data is written from the bus into the sa828 (only when r/ w is low) on the falling edge of ds (providing cs i s low). controlling the sa828 the sa828 is controlled by loading data into two 24-bit registers via the microprocessor interface. these registers are the initialisation register and the control register. the initialisation register would normally be loaded before motor operation (i.e., prior to the pwm outputs being activated) and sets up the basic operating parameters associated with the motor and inverter. this data would not normally be updated during motor operation. the control register is used to control the pwm outputs (and hence the motor) during operation e.g., stop/start, speed, forward/reverse etc. and would normally be loaded and changed only after the initialisation register has been loaded. as the motel bus interface is restricted to an 8-bit wide format, data to be loaded into either of the 24-bit registers is first written to three 8-bit temporary registers r0, r1 and r2 before being transferred to the desired 24-bit register. the data is accepted (and acted upon) only when transferred to one of the 24-bit registers. transfer of data from the temporary registers to either the initialisation register or the control register is achieved by a write instruction to a dummy register. writing to dummy register r3 results in data transfer from r0, r1 and r2 to the control register, while writing to dummy register r4 transfers data from r0, r1 and r2 to the initialisation register. it does not matter what data is written to the dummy registers r3 and r4 as they are not real registers. it is merely the write instruction to either of these registers which is acted upon in order to load the initialisation and control registers. sa828 6 pdy f carr x 512 counter reset when the cr bit is active (i.e., iow) the internal power frequency phase counter is set to 0 degrees for the red phase. it will remain at 0 degrees until the cr bit is released (i.e., high). control register function this 24-bit register contains the parameters that would normally be modified during pwm cycles in order to control the operation of the motor. the parameters set in the control register are as follows: power frequency (speed) allows the power frequency of the pwm outputs to be adjusted within the range specified in the initialisation register forward/reverse allows the direction of rotation of the ac motor to be changed by changing the phase sequence of the pwm outputs. power frequency amplitude by altering the widths of the pwm output pulses while maintaining their relative widths, the amplitude of the power waveform is effectively altered whilst maintaining the same power frequency. overmodulation allows the output waveform amplitude to be doubled so that a quasi-squarewave is produced. a combination of overmodulation and a lower power frequency can be used to achieve rapid braking in ac motors. output inhibit allows the outputs to be set to the low state while the pwm generation continues internally. useful for temporarily inhibiting the outputs without having to to change other register contents. the power frequency range is a function of the carrier waveform frequency ( f carr ) and a multiplication factor m , determined by the 3-bit frs word. the value of m is determined as shown in table 5. frs word value of m 000 1 001 2 010 4 011 8 100 16 101 32 table 5 values of carrier frequency multiplicaion factor m 110 64 the power frequency range, f range , is then given by: where f carr = carrier frequency and m = 1, 2, 4, 8, 16, 32 or 64 (as set by frs). f carr 384 f range = x m x x pdy 5 pdy 4 pdy 3 pdy 2 pdy 1 pdy 0 ? ? ? ? ? ? ? ? ? ? dont care pulse delay select word pdy 5 = msb pdy 0 = lsb fig. 7 temporary register r2 pdy word value of pdy 000000 64 ...etc... ...etc... 111110 2 table 6 values of pdy 111111 1 the pulse delay time, t pdy , is then given by: where pdy = 1- 64 (as set by pdy) and f carr = carrier frequency. fig 8 shows the eftect of the pulse delay circuit. it should be noted that as the pulse delay circuit follows the pulse deletion circuit (see fig. 2), the minimum pulse width seen at the pwm outputs will be shorter than the pulse deletion time set in the initialisation register. the actual shortest pulse generated is given by t pd C t pdy . pulse delay time the pulse delay time affects all six pwm outputs by delaying the rising edges of each of the outputs by an equal amount. the pulse delay time is a function of the carrier waveform frequency and pdy , defined by the 6-bit pulse delay time select word (pdy). the value of pdy is selected as shown in table 6. fig. 8 effect of pulse delay on pwm pulse train pwm signal required at inverter output t pdy t pdy t pdy t pdy output signal to drive top switch inverter arm output signal to drive bottom switch inverter arm t pdy = pulse delay time t pdy = cr pdt 6 pdt 5 pdt 4 pdt 3 pdt 2 pdt 1 pdt 0 ? ? ? ? ? ? ? counter reset pulse deletion time select word pdt 6 = msb pdt 0 = lsb fig. 9 temporary register r0 pulse deletion time to eliminate short pulses the true pwm pulse train is passed through a pulse deletion circuit. the pulse deletion circuit compares pulse widths with the pulse deletion time set in the initialisation register. lf a pulse (either positive or negative) is greater than or equal in duration to the pulse deletion time, it is passed through unaltered, otherwise the pulse is deleted. the pulse deletion time, t pd , is a function of the carrier wave frequency and pdt , defined by the 7-bit pulse deletion time word (pdt). the value of pdt is selected as shown in table 7. pdt word value of pdt 0000000 128 ...etc... ...etc... 1111110 2 table 7 values of pdt 1111111 1 the pulse deletion time, t pd , is then given by: where pdt = 1-128 (as set by pdt) and f carr = carrier frequency. fig. 10 shows the effect of pulse deletion on a pure pwm waveform. t pd = pdt f carr x 512 7 sa828 fig. 10 the effect of the pulse deletion circuit pwm signal before pulse deletion sa828 8 sa828 programming example the following example assumes that a master clock of 12288 mhz is used (12288 mhz crystals are readily available). this clock frequency will allow a maximum carrier frequency of 24 khz and a maximum power frequency of 4 khz. initialisation register programming example a power waveform range of up to 250hz is required with a carrier frequency of 6khz, a pulse deletion time of 10 m s and an underlap of 5 m s. 1. setting the carrier frequency the carrier frequency should be set first as the power frequency, pulse deletion time and pulse delay time are all defined relative to the carrier frequency. we must calculate the value of n that will give the required carrier frequency: from table 4, n = 4 corresponds to a 3-bit cfs word of 010 in temporary register r1. 2. setting the power frequency range we must calculate the value of m that will give the required power frequency: from table 5, m = 16 corresponds to a 3-bit frs word of 100 in temporary register r1. 3. setting the pulse delay time as the pulse delay time affects the actual minimum pulse width seen at the pwm outputs, it is sensible to set the pulse delay time before the pulse deletion time, so that the effect of the pulse delay time can be allowed for when setting the pulse deletion time. 12288 x 10 6 512 x 6 x 10 3 t n = = = 4 amp 7 amp 6 amp 5 amp 4 amp 3 amp 2 amp 1 amp 0 ? ? ? ? ? ? ? amplitude select word amp 7 = msb amp 0 = lsb fig.14 temporary register r2 amplitude selection the power waveform amplitude is determined by scaling the amplitude of the waveform samples stored in the rom by the value of the 8-bit amplitude select word (amp). the percentage amplitude control is given by: where a = decimal value of amp. power-up c0nditions all bits in both the initialisation and control registers power- up in an unidentified state. holding rst low or using the set trip input will ensure that the pwm outputs remain inactive (i.e., low) until the device is initialised. power amplitude, a power = x 100% f carr = k 512 x f carr f range = x m t m = = = 16 f carr 384 f range x 384 f carr 250 x 384 6 x 10 3 a 255 k 512 x n however, the value of pdy must be an integer. as the purpose of the pulse delay is to prevent shoot-through (where both top and bottom arms of the inverter are on simultaneously), it is sensible to round the pulse delay time up to a higher, rather than a lower figure. thus, if we assign the value 16 to pdy this gives a delay time of 52 m s. from table 6, pdy = 16 corresponds to a 6-bit pdy word of 110000 in temporary register r2. 4. setting the pulse deletion time in setting the pulse deletion time (i.e., the minimum pulse width) account must be taken of the pulse delay time, as the actual minimum pulse width seen at the pwm outputs is equal to t pd C t pdy . therefore, the value of the pulse deletion time must, in this instance, be set 52 m s longer than the minimum pulse length required minimum pulse length required = 10 m s \ t pd to be set to 10 m s + 52 m s = 152 m s now, t pdt = f pd x f carr x 512 = 152 x 10 C6 x 6 x 10 3 x 512 = 467 t pd = again, pdt must be an integer and so must be either rounded up or down C the choice of which will depend on the application. assuming we choose in this case the value 46 for pdt , this gives a value of t pd , of 15 m s and an actual minimum pulse width of 15 C 52 m s = 98 m s. from table 7, pdt = 46 corresponds to a value of pdt, the 7-bit word in temporary register r0 of 1010010. the data which must be programmed into the three temporary registers r0, r1 and r2 (for transfer into the initialisation register) in order to achieve the parameters in the example given, is shown in fig. 15. fig. 15 1 1 0 1 0 0 1 0 cr pdt 6 pdt 5 pdt 4 pdt 3 pdt 2 pdt 1 pdt 0 temporary register r0 1 0 0 x x 0 1 0 temporary register r1 frs 2 frs 1 frs 0 x x cfs 2 cfs 2 cfs 2 x x 1 1 0 0 0 0 temporary register r2 x x pdy 5 pdy 4 pdy 3 pdy 2 pdy 1 pdy 0 we must calculate the value of pdy that will give the required pulse delay time: t pdy = t pdy x f carr x 512 = 5 x 10 C6 x 6 x 10 3 x 512 = 154 pdy f carr x 512 t pdy = pdt f carr x 512 9 sa828 fig. 17 typical sa828 programming routine write r1 write r2 write r4 power on write r0 rst 0 rst - 1 change control data ? change initialisation data ? yes no yes no write r1 write r2 write r3 write r0 write r1 write r2 write r3 write r0 write initialisation data write to control register inhibiting pwm outputs before completing reset cycle enable pwm outputs write control data ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? control register programming example the control register would normally be updated many times while the motor is running, but just one example is given here. it is assumed that the initialisation register has already heen programmed with the parameters given in the previous example. a power waveform of 100hz is required with a pwm waveform amplitude of 80% of that stored in the rom. the phase sequence should be set to give forward motor rotation.the outputs should be enabled and no overmodulation is required. 1. setting the power frequency the power frequency, f power , can be selected to 12-bit accuracy (i.e 4096 equal steps) from 0hz to f range as defined in the initialisation register. in this case, with f range = 250hz, the power frequency can be adjusted in increments of 006hz. we can only have pfs as an integer, so if we assign pfs = 1638 this gives f power = 99.97 hz.the 12-bit binary equivalent of this value gives a pfs word of 011001100110 in temporary registers r0 and r1. 2. setting overmodulation, forward/reverse, output inhibit overmodulation is not required therefore om = 0. forward motor control is required (i.e., the phase sequence of the pwm outputs should be red-yellow-blue) therefore forward/ reverse bit f/r = 0. output inhibit should be inactive (i e., the outputs should be active), therefore inh= 1. these bits are all set in temporary register r1. 3. setting the power waveform amplitude a power x 255 100 a power =x 100% 0 1 1 0 0 0 1 1 temporary register r0 0 0 1 x 0 1 1 0 temporary register r1 1 1 0 0 temporary register r2 1100 pfs 7 pfs 6 pfs 5 pfs 4 pfs 3 pfs 2 pfs 1 pfs 0 f / r om inh x pfs 11 pfs 10 pfs 9 pfs 8 amp 7 amp 6 amp 5 amp 4 amp 3 amp 2 amp 1 amp 0 fig. 16 the 8-bit binary equivalent of this value gives an amp word of 11001100 in temporary register r2. the data which must be programmed into the three temporary registers r0, r1 and r2 (for transfer into the control register) in order to achieve the parameters in the example given, is shown in fig. 16. 80 x 255 100 t a = = = 204 f power x 4096 f range f range 4096 t pfs = = = 16384 100 x 4096 250 a 225 f power = x pfs sa828 10 product designation two standard options exist, defining waveform shape. these are designated sa828-1 and sa828-2 as follows: sa828-1 sine + third harmonic at one-sixth the amplitude of the fundamental: x(t) = a [ sin ( w t ) + sin 3( w t) ] sa828-2 pure sinewave: x(t) = a [ sin ( w t )] additional wave shapes can be implemented to order, provided they are symmetrical about the 90 , 180 and 270 axes. contact your local mitel semiconductor customer service centre for further details. 1 6 hardware input/output functions set output trip (set trip input) the set trip input is provided separately from the microprocessor interface in order to allow an external source to override the microprocessor and provide a rapid shutdown facility. for example, logic signals from overcurrent sensing circuitry or the microprocessor watchdog might be used to activate this input. when the set trip input is taken to a logic high, the output trip latch is activated. this results in the trip output and the six pwm outputs being latched low immediately. this condition can only be cleared by applying a reset cycle to the rst input. it is essential that when not in use set trip is tied low and isolated from potential sources of noise; on no account should it be left floating. set trip is latched internally at the master clock rate in order to reduce noise sensitivity. output trip status ( trip output) the trip output indicates the status of the output trip latch and is active low. reset ( rst input) the rst input performs the following functions when active (low): 1. all pwm outputs are forced low (if not already low) thereby turning off the drive switches. 2. all internal counters are reset to zero (this corresponds to 0 for the red phase output). 3. the rising edge of rst reactivates the pwm outputs resetting the output trip and setting the trip output high C assuming that the set trip input is inactive (i.e. iow). a sixth register, r5, located at a2:o = 101 is used to place the device into a factory test mode. this is achieved by writing dummy data to r5 immediately after rst goes high. care must be exercised to ensure that the microprocessor/controller cannot write to this register. zero phase pulses (zppr, zppy and zppb outputs) the zero phase pulse outputs provide pulses at the same frequency as the power frequency with a 1 : 2 mark-space ratio. when in the forward mode of operation the falling edge of zppr corresponds to 0 for the red phase, the falling edge of zppy to 0 for the yellow phase and the zppb falling edge to 0 for the blue phase. in the reverse mode, the rising edge of a zero phase pulse corresponds to 0 for the relevant phase pwm output. waveform sampling synchronisation (wss output) this output provides a square wave signal of 50% duty cycle at a frequency 1536 times higher than the fundamental of the power waveform. each successive pulse of wss corresponds to the sa828 reading the next location of the waveform rom. it may be used in conjunction with the zpp signals to monitor the position of the machine rotor and may form part of a closed loop control system such as slip compensation. clock (clk input) the clk input provides a timing reference used by the sa828 for all timings related to the pwm outputs. the microprocessor interface, however, derives all its timings from the microprocessor and therefore the microprocessor and the sa828 may be run either from the same or from different clocks. waveform definition the waveform amplitude data used to construct the pwm output sequences is read from the internal 384x8 rom. this contains the 90 span of the waveform as shown in fig. 18. each successive 8-bit sample linearly represents the instantaneous amplitude of the waveform. it is assumed that the waveform is symmetrical about the 90 , 180 and 270 axes. the sa828 reconstructs the full 360 waveform by reading the 0 -90 section held in rom and assigning negative values for the second half of the cycle. these samples are used to calculate the instantaneous amplitudes for all three phases, which will be 120 transposed in the normal r-y-b orientation for forward rotation or b-y-r for reverse rotation. the 384 8-bit samples are regularly spaced over the 0 to 90 span, giving an angular resolution of approximately 023 . waveform segment 0 - 30 3023 - 60 6023 - 8977 sample number 0 - 127 128 - 255 256 - 383 table 8 90 of the 360 cycle is divided into 384 8-bit samples fig. 18 90 sample of typical power waveform value of 8-bit sample 0 45 90 255 0 phase (384-bit resolution) power waveform 11 sa828 fig. 19 a typical sa828 application 3-phase variable voltage, variable frequency waveform 3-phase ac induction motor inverter isolator ttl level pwm waveforms 6 6 fast shutdown sa828 dc link e + single or 3-phase power supply r y b rectifier and smoothing data / address bus (ad 0 -ad 7 ) 8 microprocessor or microcontroller with on-chip rom and ram optional external rom optional external ram sa828 12 13 sa828 package details dimensions are shown thus: mm (in). for further package information, please contact your local customer service centre. 2?6/2?4 (0?93/0?04) 28 leads at 1?7 (0?50) nom. spacing 17?0/18?0 (0?97/0?13) 0?0/0?0 (0?04/0?12) 0?1/1?7 (0?16/0?50) 0?5/0?1 (0?10/0?28) 0?3/0?3 (0?09/0?13) 28-lead miniature plastic dil - mp28 0?4 (0?29) max. 45 0?6/0?8 (0?14/0?19) 7?0/7?0 (0?91/0?99) 10?0/10?4 (0?94/0?19) 1 28 spot ref. chamfer ref. 0-8 notes 1. controlling dimensions are inches. 2. this package outline diagram is for guidance only. please contact your mitel semiconductor customer service centre for further information. 051 (002) min 038/061 (0015/0024) 3810 (15) max 28-lead plastic dil C dp28 1 28 305 (0120) min pin 1 ref notch 1473 (058) max 508/(0200) max 023/041 (0009/0016) 15.24 (06) nom ctrs 28 leads at 254 (010) nom. spacing 114/165 (0045/0065) notes 1. controlling dimensions are inches. 2. this package outline diagram is for guidance only. please contact your mitel semiconductor customer service centre for further information. seating plane sa828 14 internet: http://www.gpsemi.com customer service centres l france & benelux les ulis cedex tel: (1) 69 18 90 00 fax : (1) 64 46 06 07 l germany munich tel: (089) 419508-20 fax : (089) 419508-55 l italy milan tel: (02) 6607151 fax: (02) 66040993 l japan tokyo tel: (03) 5276-5501 fax: (03) 5276-5510 l korea seoul tel: (2) 5668141 fax: (2) 5697933 l north america scotts valley, usa tel: (408) 438 2900 fax: (408) 438 5576/6231 l south east asia singapore tel:(65) 3827708 fax: (65) 3828872 l sweden stockholm tel: 46 8 702 97 70 fax: 46 8 640 47 36 l taiwan, roc taipei tel: 886 2 25461260 fax: 886 2 27190260 l uk, eire, denmark, finland & norway swindon tel: (01793) 726666 fax : (01793) 518582 these are supported by agents and distributors in major countries world-wide. ? mitel corporation 1998 publication no. ds4226 issue no. 2.0 november 1996 technical documentation C not for resale. printed in united kingdom headquarters operations mitel semiconductor cheney manor, swindon, wiltshire sn2 2qw, united kingdom. tel: (01793) 518000 fax: (01793) 518411 mitel semiconductor 1500 green hills road, scotts valley, california 95066-4922 united states of america. tel (408) 438 2900 fax: (408) 438 5576/6231 this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regard ing the capability, performance or suitability of any product or service. the company reserves the right to alter without prior notice the specification, design or price of any product or service. information con cerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to f ully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, w hich are available on request. all brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respec tive owners. |
Price & Availability of SA8281MP1S
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |